/*******************************************************************************
*                                    ZLG
*                         ----------------------------
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* Copyright (c) 2001-2021 Guangzhou ZHIYUAN Electronics Co., Ltd.
* All rights reserved.
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#ifndef __HC32F4A0_REGS_CMU_H
#define __HC32F4A0_REGS_CMU_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/
#include <stdio.h>
#include "hc32f4a0_regs_base.h"

/**
 * \brief 系统时钟源切换位掩码
 * 000: HRC作为系统时钟
 * 001: MRC作为系统时钟
 * 010: LRC作为系统时钟
 * 011: XTAL作为系统时钟
 * 100: XTAL32作为系统时钟
 * 101: PLLH作为系统时钟
 */
#define CMU_CKSWR_CKSW           (0x07U)

#define CMU_OSCSTBSR_PLLHSTBF    (0x20U)

/* \brief CMU PLLH 控制寄存器位定义*/
#define CMU_PLLHCR_PLLHOFF       (0x01U)


/* \brief CMU SCFGR 时钟分频配置寄存器位定义  */
#define CMU_SCFGR_PCLK0S_POS     (0U)
#define CMU_SCFGR_PCLK0S         (0x00000007UL)  /* PCLK0 时钟分频选择位*/
#define CMU_SCFGR_PCLK1S_POS     (4U)
#define CMU_SCFGR_PCLK1S         (0x00000070UL)  /* PCLK1 时钟分频选择位*/
#define CMU_SCFGR_PCLK2S_POS     (8U)
#define CMU_SCFGR_PCLK2S         (0x00000700UL)  /* PCLK2 时钟分频选择位*/
#define CMU_SCFGR_PCLK3S_POS     (12U)
#define CMU_SCFGR_PCLK3S         (0x00007000UL)  /* PCLK3 时钟分频选择位*/
#define CMU_SCFGR_PCLK4S_POS     (16U)
#define CMU_SCFGR_PCLK4S         (0x00070000UL)  /* PCLK4 时钟分频选择位*/
#define CMU_SCFGR_EXCKS_POS      (20U)
#define CMU_SCFGR_EXCKS          (0x00700000UL)  /* ExMC 时钟分频选择位*/
#define CMU_SCFGR_HCLKS_POS      (24U)
#define CMU_SCFGR_HCLKS          (0x07000000UL)  /* HCLK 时钟分频选择位*/

/* \brief PLLH M 分频范围定义*/
#define CLK_PLLHM_DIV_MIN        (1UL)
#define CLK_PLLHM_DIV_MAX        (4UL)

/* \brief PLLH N 倍频范围定义*/
#define CLK_PLLHN_MULTI_MIN      (25UL)
#define CLK_PLLHN_MULTI_MAX      (150UL)

/* \brief PLLH R 分频范围定义*/
#define CLK_PLLHR_DIV_MIN        (2UL)
#define CLK_PLLHR_DIV_MAX        (16UL)

/* \brief PLLH Q 分频范围定义*/
#define CLK_PLLHQ_DIV_MIN        (2UL)
#define CLK_PLLHQ_DIV_MAX        (16UL)

/* \brief PLLH P 分频范围定义*/
#define CLK_PLLHP_DIV_MIN        (2UL)
#define CLK_PLLHP_DIV_MAX        (16UL)

/* \brief PLLH P/Q/R 频率范围定义*/
#define CLK_PLLH_FREQ_MIN        (40UL*1000UL*1000UL)
#define CLK_PLLH_FREQ_MAX        (240UL*1000UL*1000UL)

/* \brief PLLH VCO IN 频率范围定义*/
#define CLK_PLLH_VCO_IN_MIN      (8UL*1000UL*1000UL)
#define CLK_PLLH_VCO_IN_MAX      (24UL*1000UL*1000UL)

/* \brief PLLH VCO OUT 频率范围定义*/
#define CLK_PLLH_VCO_OUT_MIN     (600UL*1000UL*1000UL)
#define CLK_PLLH_VCO_OUT_MAX     (1200UL*1000UL*1000UL)

/* \brief HC32F4A0 时钟控制器寄存器*/
typedef struct hc32f4a0_cmu_reg {
    volatile uint8_t  XTAL32CR;
    uint8_t           RESERVED0[3];
    volatile uint8_t  XTAL32CFGR;
    uint8_t           RESERVED1[15];
    volatile uint8_t  XTAL32NFR;
    uint8_t           RESERVED2[7];
    volatile uint8_t  LRCCR;
    uint8_t           RESERVED3[3];
    volatile uint8_t  RTCLRCCR;
    uint8_t           RESERVED4[3];
    volatile uint8_t  LRCTRM;
    uint8_t           RESERVED5[7];
    volatile uint8_t  RTCLRCTRM;
    uint8_t           RESERVED6[2123];
    volatile uint8_t  XTALCFGR;
    uint8_t           RESERVED7[29591];
    volatile uint16_t PERICKSEL;
    volatile uint16_t I2SCKSEL;
    uint8_t           RESERVED8[4];
    volatile uint8_t  CANCKCFGR;
    uint8_t           RESERVED9[7];
    volatile uint32_t SCFGR;
    volatile uint8_t  USBCKCFGR;
    uint8_t           RESERVED10[1];
    volatile uint8_t  CKSWR;              /* 系统时钟源切换寄存器*/
    uint8_t           RESERVED11[3];
    volatile uint8_t  PLLHCR;             /* PLLH控制寄存器*/
    uint8_t           RESERVED12[3];
    volatile uint8_t  PLLACR;
    uint8_t           RESERVED13[3];
    volatile uint8_t  XTALCR;
    uint8_t           RESERVED14[3];
    volatile uint8_t  HRCCR;
    uint8_t           RESERVED15[1];
    volatile uint8_t  MRCCR;
    uint8_t           RESERVED16[3];
    volatile uint8_t  OSCSTBSR;            /* 时钟源稳定状态寄存器*/
    volatile uint8_t  MCO1CFGR;
    volatile uint8_t  MCO2CFGR;
    volatile uint8_t  TPIUCKCFGR;
    volatile uint8_t  XTALSTDCR;
    volatile uint8_t  XTALSTDSR;
    uint8_t           RESERVED17[31];
    volatile uint8_t  MRCTRM;
    volatile uint8_t  HRCTRM;
    uint8_t           RESERVED18[63];
    volatile uint8_t  XTALSTBCR;
    uint8_t           RESERVED19[93];
    volatile uint32_t PLLHCFGR;            /* PLLH配置寄存器*/
    volatile uint32_t PLLACFGR;
} hc32f4a0_cmu_reg_t;


#define HC32F4A0_CMU    ((hc32f4a0_cmu_reg_t *)HC32F4A0_CMU_BASE)

#ifdef __cplusplus
}
#endif  /* __cplusplus  */

#endif  /* __HC32F4A0_CMU_REG_H */

